A communication device such as a cellular radiotelephone can contain many control devices that can interface to a variety of peripheral devices. Normally, control-to-peripheral communication can be thought of in a master/slave relationship where a master unit can control operation of a peripheral unit through a communication bus, such as a serial peripheral interface (SPI) as is known in the art. The communication bus and peripheral include internal components, which are able to receive information in bit form from other devices and to create a data field from the received information. All messages sent over the communication bus contain data fields. Although the messages are mainly for information transfer and control, the data fields can contain header bits for message handling information, including a priority field, a register select field, and an address field designating the address or addresses of the device(s) originating or receiving the message.
Generally, a peripheral device can be considered as an external device that attaches to a main device, such as a printer connected to a computer for example. However, this is a simplified view, and, in the context of a radiotelephone, a master (control) unit or slave (peripheral) unit can be considered on a component level. For example, an accessory can be connected to a radiotelephone wherein a component in the radiotelephone can be slaved to a controller on the accessory. One example of this is having an audio accessory plug into the radiotelephone with the accessory controlling an audio amplifier circuit in the radiotelephone.
In addition, components entirely within the radiotelephone can have a master/slave relationship. One example of this is having the main processor of the radiotelephone act as a master unit and a memory module, such as a serial EEPROM, act as a slave unit. Another example is having the main processor of the radiotelephone act as a master unit and a transceiver integrated circuit or digital signal processor act as a slave unit. A further example is having the main processor of the radiotelephone act as a master unit and an amplifier circuit act as a slave unit. All of these relationships can be controlled using a communication interface.
FIG. 1 shows a prior art system architecture using a synchronous control interface or SPI in a master/slave(s) configuration. In this typical configuration, the master device 10 sends serial data over a communication bus 14 to a slave device 12 such as a transceiver IC, serial EEPROM, or amplifier, for example. Basically, the SPI is a master/slave arrangement that allows two shift registers 16,18 to exchange data. Since it is not really “peer-to-peer”, like a universal asynchronous receiver/transmitter, it is typically used by a microcontroller to send data to “dumb” devices. The master unit transmits the data sequentially shifted bit-by-bit into a register within the peripheral. Some of bits are data, while other bits are control bits. Generally, flow control bits, priority bits, address bits or other format bits are added to the bits shifted into the register to comprise a bus format for messages that are sent from the central processing portion of the radiotelephone. Each peripheral has a particular chip select or address that is defined during a start-up procedure, as is known in the art. The data bits in the shift register 18 are then parallel gated, through a tri-state buffer for example, into an output latch register 20.
The basic signals used on the communication bus 14 are Master Out/Slave In (MOSI), Master In/Slave Out (MISO), Serial Clock (SCK), Slave Select ({overscore (SS)}), and master signal Chip Select ({overscore (CS)}). The MOSI line is a serial data line from the master to the slave device. The MISO line is a serial data line from the slave to the master device. The SCK line is the shift register clock from the master that clocks both Master and Slave shift registers. Note that although FIG. 1 suggests one shift register 16,18 being used (on each of master and slave) for both sending and receiving data, in most implementations, separate registers can be provided. The {overscore (SS)} line of the slave 12 is shown as being driven by the {overscore (CS)} line of the master 10. This low true signal is used to enable the SPI peripheral on the slave device. It would typically gate SCK on or off in the slave, and also tri-state or enable MISO from the slave device. In other words, when {overscore (SS)} is Low (asserted), MISO is enabled and SCK is gated on. Correspondingly, when {overscore (SS)} is High (de-asserted), MISO is tri-stated and SCK is gated off to stop data from coming into the slave device when it is not being selected. Alternatively, (as shown) {overscore (SS)} de-assertion inhibits the transfer of data flowing into the shift register 18 to the latch register 20 rather than directly gating the clock and disabling MISO. The end result is the same in that {overscore (SS)} de-assertion disables the SPI function of the slave device.
The reason that MISO must be tri-stated is that the SPI typically supports multiple devices, each sharing the same MOSI, MISO, and SCK, but having individual chip selects. The de-assertion of {overscore (SS)} for each device must cause MISO for that device to tri-state, otherwise contention would occur when more than one slave device is connected to MISO. It should also be noted that some SPI slave devices may be “write only” and would not have a MISO line.
Basic SPI operation is as follows. Initially, {overscore (CS)} is de-asserted and SCK is idle (high or low). The Master unit 10 asserts {overscore (CS)} to the slave device 12 it wants to send data to. After some small setup delay, the master unit 10 clocks out data on MOSI and reads in data on MISO (if available), using the SCK signal. The same clock edge used to transfer MOSI data to the slave shift register 18 is also use to latch in data from the slave MISO into the master shift register 16. The SPI configuration bits, however, allow for high or low going edges to be used. Typical transfers would involve 8 or 16 bits. In more sophisticated designs, much larger SPI queues are used, allowing for 64 bytes or more to be transferred. When the transfer is finished (i.e., the last bit of the last word is shifted in/out), the SCK signal idles (high or low) and a short time later {overscore (CS)} is de-asserted again. In the configuration shown, only the master unit can initiate a data transfer. However, in configurations where there are two master units vying for control of one slave peripheral, there are different considerations.
In those architectures where there are two or more processors present, prior art solutions provide for arbitration for control of a single SPI slave device. This allows certain functions of the slave device to be enabled/disabled by either processor. Unfortunately, the standard SPI architecture uses only a single SPI slave port per slave device. Any arbitration between two masters and one slave would have to be via external multiplexers 22 between the master's SPI outputs and the slave's inputs, as shown in FIG. 2. The drawback to this scheme is that only one master unit can access the slave device at a time. In addition, the software arbitration creates complexities in the software architecture.
A practical example of the problems caused by lack of a dual access SPI is the case where a main processor controls a component, such as an audio amplifier for example, via SPI messages,. If an adjunct processor such as a second separate microprocessor running an operating system such as Microsoft Windows CE™ (WinCE™) is added, it would be advantageous to allow control of the audio amplifier, or other user interface, by this adjunct processor. Since the main processor is also used for other real-time or system critical functions of a radiotelephone, it would not be appropriate or efficient to have the adjunct processor control the SPI. It would instead be necessary for the adjunct processor to send messages to the main processor to enable the particular user interface of interest, using another interface such as a UART.
Accordingly, it would be desirable if a peripheral interface were configured so that multiple master control units could control the peripheral. It would also be beneficial if this could be accomplished in a transparent manner. Moreover, it would also be of benefit to accomplish this without the use of control signal multiplexing, in order to reduce complexity and to use the radiotelephone components more efficiently.